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Security in QuickLogic Devices

Authored on: Feb 23, 2004 by Mehul Kochar

Technical Paper / Product Paper

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Design security is vital in this age when intellectual property and product development costs continue to increase. Whether you are creating fully programmable FPGAs or customized ASICs, the features differentiating your products from the competitors' are often designed into an Integrated Circuit. Therefore, your design can be easily stolen by competitors or hackers who can then market it as their own.

When it comes to development time, cost, and risk, FPGAs have several advantages over ASICs. Because FPGAs do not require custom mask sets and fabrication lead times, design cycle times often span for weeks or months instead of years, as they are with ASICs.

High mask set costs, expensive ASIC development tools, and wafer foundry volume commitments often make custom ASIC development an unfeasible business decision. Since FPGA designs can be changed at an engineer's desk several times in one day, product marketing requirements and development bugs can be fixed in a very short period of time; these design changes are not possible once an ASIC has taped out. Therefore, FPGAs ultimately reduce the development risks associated with the fixed functionality ASICs. These obvious FPGA advantages fuel the growing popularity of FPGAs in all market segments, including military, encryption, and security applications. As a result, the security of the underlying FPGA technology has become an important issue.

This document explains the different methods that can be used to steal designs (like reverse engineering and cloning) and how QuickLogic's patented ViaLink technology can protect a design from being stolen. This document also compares the ViaLink technology to other FPGA technologies and presents the advantages of using ViaLink over other technologies.

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