Silicon Design Chain Cooperation Enables Nanometer Chip Design
Recognizing the problems with silicon design methodology over the past several years, EDA vendors and foundries have introduced products and services directly aimed at simplifying both front-end and back-end chip design. However, these efforts were often divided because of the process that separates the end of design from the beginning of chip manufacturingsilicon processing. For nanometer designs at 130 nm and below, TSMC has developed Design Reference Flow 4.0, which concentrates on back-end (post-synthesis) design and incorporates Cadence design technologies and several design techniques to increase the probability of first-time silicon success.
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