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A Discussion of the Block Floating-Point FFT Implementation on Fixed-point DSPs

Authored on: Apr 21, 2006 by Arun Chhabra and Ramesh A. Iyer

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Block floating-point (BFP) implementation provides an innovative method of floating-point emulation. This paper implements the BFP algorithm for the Fast Fourier Transform (FFT) algorithm. The BFP algorithm as it applies to the FFT allows fractional signal gain adjustment in a fixed-point environment by using a block representation of input values of block size N to an N-point FFT. This algorithm is applied repetitively to all stages of the FFT. The elements within a block are further represented by their respective mantissas and a common exponent assigned to the block. This method allows for aggressive scaling with a single exponent while retaining greater dynamic range in the output. This paper discusses the BFP FFT and demonstrates its implementation in assembly language. The implementation is carried out on a fixed-point digital signal processor (DSP). The fixed-point BFP FFT results are contrasted with the results of a floating-point FFT of the same size implemented with MATLAB. For applications where the FFT is a core component of the overall algorithm, the BFP FFT can provide results approaching floating-point dynamic range on a low-cost fixed-point processor. Most DSP applications can be handled with fixed-point representation. However, for those applications that require extended dynamic range but do not warrant the cost of a floating-point chip, a block floating-point implementation on a fixed-point chip readily provides a cost-effective solution.

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