Implementing High-Speed RLDRAM II Interfaces Using FPGAs
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Increasing I/O bandwidth requirements in the graphics, telecom and communication industries and growing PC processor speeds are fueling a need for high performance memory interfaces. This paper will focus on RLDRAM II technology and implementation of a high-speed interface in programmable logic. It will present an analysis of the memory interface and identify some of the barriers that limit interface performance. The paper will then identify techniques that a programmable logic memory controller designer can implement in order to overcome such barriers. In particular, the paper will present a case for use of embedded silicon approaches in programmable logic for automatic alignment of data strobes to data during READ and WRITE cycles. Through this paper, a memory system designer will be able to better understand RLDRAM II interfaces, and the tradeoffs between different controller interface methodologies.
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