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Multi-Core Embedded Debug for Structured ASIC Systems

Authored on: Sep 23, 2004 by Dr. Neal Stollon, Rick Leatherman, Bruce Ableidinger, and Ernie Edgar

Technical Paper / Conference Paper

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Providing in depth analysis and debug of applications that utilize multiple embedded processors and buses is a critical piece of system on a chip (SoC) design processes. While debug of a single embedded core is challenging, it is a relatively well understood problem, whereas MultiCore architectures add new considerations and complexity that must be factored into the debug solution. As core implementations become more complex, they expand both in subsystem functionality (as an example, moving from a processor core to processor + caches + bus interfaces + dedicated peripherals as a pre-integrated IP block) and in interface complexity (multiple bus interfaces to shared resources). The debug questions for embedded systems design move beyond those of "is this core working correctly" to "how do I get my application code operating more efficiently" and "how well is this part of the system interacting with other subsystems." These are problems that require a system debug focus rather than just analysis of a single core.

In this paper, a system level debug approach and architecture called MultiCore Embedded Debug (MED) is presented. MED architecture supports structured ASIC integration and diagnostics by creating a distributed subsystem of on-chip instrumentation (OCI) blocks, customized to support diverse processors, embedded logic blocks, and embedded buses. This approach provides a debug backplane to address dense and complex multi-core systems analysis. By using instrumentation blocks as resources for embedded intelligent debug operations, analysis features such as system-wide error recognition and filtering, and cross triggering and performance analysis between different subsystems of a complex architecture are supported, which are not achievable with other currently available debug strategies.

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