Multi-Core Embedded Debug for Structured ASIC Systems
In this paper, a system level debug approach and architecture called MultiCore Embedded Debug (MED) is presented. MED architecture supports structured ASIC integration and diagnostics by creating a distributed subsystem of on-chip instrumentation (OCI) blocks, customized to support diverse processors, embedded logic blocks, and embedded buses. This approach provides a debug backplane to address dense and complex multi-core systems analysis. By using instrumentation blocks as resources for embedded intelligent debug operations, analysis features such as system-wide error recognition and filtering, and cross triggering and performance analysis between different subsystems of a complex architecture are supported, which are not achievable with other currently available debug strategies.