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Using System-on-Gate-Array to Optimize SoC Design Costs

Authored on: Oct 8, 2003 by Niels Trapp and Dr. Wolfgang Schmitt

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After an extremely successful year in 2000, the electronics industry slid into a downturn in 2001 from which it has not yet recovered. Projects that called for high integration have been stopped, postponed or even totally scrapped. Development teams have been merged or assigned to other projects and the next killer application is nowhere in sight, least of all in the telecommunications segment. In some segments, the mood is skeptical because many euphoric market forecasts have simply failed to materialize. The current situation is made more difficult for the semiconductor industry by the heavy investment already made in advanced 90 nm process technology. What do you do if the matching investments on the project side are not forthcoming, because the money for these has yet to be earned? In recent years, NEC Electronics has committed considerable resources to solving the problem of cost-efficient, customized system integration. The goal was to make SoC designs, hitherto only feasible in high-volume applications, available to a wider group of applications and customers. The outcome was a product family that resolves the problem of cost pressure and provides a very fast and straightforward route to complex SoC integration. The System-on-Gate-Array is NEC Electronics' platform concept for ARM core-based SoCs that offers customers the solutions they need at costs they can afford.

Reprinted in its entirety from ARM IQ Vol. 2, No. 2



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