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Improving HW/SW Co-Verification with SoC Verification Matrix

Authored on: May 26, 2004 by Jason Andrews

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Verification efficiency is the latest topic being discussed among engineers and EDA vendors. In order to work smarter, engineers can make improvements to the overall verification process, by automating best practices rather than focusing on incremental speed improvements in individual point tools.

This article describes how engineers doing ARM SoC verification can be more efficient through automated process solutions based on a single, reconfigurable verification system, applications, and an unified methodology to allow engineers to execute hardware and software tests with a flexible mix of performance and debugging.

Reprinted in its entirety from ARM IQ Vol. 3, No. 2

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