Complex SoC Verification Designed for Reuse
The key to improving designer productivity is reducing the amount of time designers spend in test creation and design verification, which can be done with extensive reuse of components and tests. This article will explore a new methodology for reuse and scaleability of SoC components and tests. It will highlight the key components in this new verification methodology and how design teams can use the SystemC verification library to take advantage of this new approach to verification reuse.
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