datasheets.com EBN.com EDN.com EETimes.com Embedded.com PlanetAnalog.com TechOnline.com  
Events
UBM Tech
UBM Tech
Welcome Guest Log In | Register

Hierarchical Implementation of the ARM Cortex-A9 MPCore with Synopsys' Galaxy Design Platform

Authored on: Oct 31, 2008 by Saran Kumar Seethapathi and Subrata Kumar

Technical Paper

0 0
More InfoLess Info

This article describes how the design planning features of IC Compiler in Synopsys Galaxy Design Platform can be deployed for the implementation of the embedded ARM Cortex-A9 MPCore multicore processor. The ARM Cortex-A9 multicore processor lends itself well to a hierarchical implementation approach; providing runtime improvements, better performance and partitioning for low-power design.

The article details how IC Compiler has been used for top-level partitioning. Areas such as processor floorplanning, block partitioning, block pin assignment, constraint budgeting and implementation strategies for each of the individual cores and top level implementation will be discussed in detail.

Finally, the article will also explain the strategies involved in concurrent block level and top-level implementation using advanced Interface Logic Models to achieve the best possible performance targets.

Reprinted in its entirety from ARM IQ Vol. 7, No. 3, 2008

View
 
0 comments
write a comment

Please Login

You will be redirected to the login page

×

Please Login

You will be redirected to the login page

×

Please Login

You will be redirected to the login page