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A Platform-based Low-Power Design Flow for an Advanced Mobile Applications Processor

Authored on: Mar 11, 2009 by Albert Chen

Technical Paper

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Low-power has become a focal point for SoC designers. Advanced techniques such as multi-supply voltages, power gating, and dynamic voltage scaling are conceptually easy to understand, but difficult to implement in practice.

Faraday, a top-tier ASIC service provider, offers successful low-power SoC designs across multiple market segments, using a proven, platform-based low-power methodology incorporating the Common Power Format (CPF) as a fundamental enabling technology

Reprinted in its entirety from ARM IQ Vol. 7, No. 4, 2008

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