High-Speed ADC Selection for Digital Predistortion Transmitters
High-bandwidth, third-generation (3G) wireless communications standards such as CDMA2000, WCDMA and WiMAX place stringent performance requirements on transmitters, particularly power amplifiers (PAs).
The PA generally represents a large fraction of the total subsystem cost, as well as the power dissipation in a base station. Several techniques can be employed to improve the linearity of the transmitter while still using a PA with higher nonlinearity but higher efficiency, which in turn lowers cost and power dissipation. This paper discusses one such technique: the Digital Predistortion (DPD) architecture. The paper provides an overview of the DPD and discusses analog-to-digital (ADC) sample rates, ADC linearity, and ADC signal-to-noise ratio (SNR).