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On-chip System Bus Performance Analysis

Authored on: Jun 16, 2006 by John LaVere

Technical Paper / Conference Paper

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A key goal in designing and using a system-on-a-chip embedded controller product is to effectively match the implementation of the on-chip bus architecture and functional blocks with the data flow and performance requirements of targeted applications. This paper will discuss an example embedded processor and a selected set of test applications to demonstrate how an integrated bus monitor is used for characterizing on-chip data flows. It will show how to define to create test cases, instrument the test bench and programs the bus monitor to measure bandwidth and latency performance of bus transaction traffic between bus agents, including the effects of other concurrent bus traffic.

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