SOC Hardware-Software Co-Development
Embedded software historically is developed after the hardware is available and software is debugged using ICE or JTAG. This design approach is limiting for control-dominated SOC designs where the SOC performance is dictated not by hardware or software components but the interfaces among these components. This paper proposes a pragmatic approach to solving this problem by using clockaccurate C simulation models of the whole chip for embedded software development earlier in the design cycle. This approach uses current tools for software and hardware development and provides an opportunity to change the hardware components and architecture by earlier integration of hardware with the software. Such an approach is critically needed for high performance communication and networking SOCs that typically contain multiple processors, coprocessors and high-speed memory systems.