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Fixed-Point DSP Algorithm Implementation

Authored on: Jul 5, 2006 by RC Cofer

Technical Paper / Conference Paper

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Digital Signal Processors are a natural choice for cost-sensitive, computationally intensive applications. With 100+ MIPS (Million Instructions Per Second) performance available in the $5 range, fixed-point DSP processor implementations can be very attractive. However, since fixed-point designs are often perceived as more challenging than floating-point or conventional processor designs many designers avoid considering fixed-point DSP implementations. This class presents the critical fixed-point DSP design issues which challenge designers new to fixed-point DSP algorithm implementation. The paper presents practical design examples and clarifies fixed-point DSP terminology. Topics include fixed vs. floating-point design, precision and accuracy, I/O quantization, dynamic range and error sources, fixed-point numeric representation and arithmetic, scaling, truncation effects, filter coefficient quantization effects, avoiding overflow, minimizing roundoff noise, and analyzing algorithms for potential problem areas.

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