Design Con 2015
Welcome Guest Log In | Register

Code Optimization Techniques for High Performance Pipelined Processors

Authored on: Jun 29, 2007 by Abhay Kataria and Amey Deosthali

Technical Paper / Conference Paper

0 0
More InfoLess Info

One of the key features of a high performance embedded processor is a multistage instruction pipeline. As the processor complexity increases, the need for software scheduling and optimization schemes becomes inevitable. Developing optimized code for pipelined processors requires a thorough understanding of the processor's pipeline structure and the latencies associated with each instruction. This paper discusses various optimization techniques and software scheduling schemes, and illustrates them using examples on the TMS320C5510 DSP processor, ST Microelectronics' ST10 microcontroller, and the LSI402ZX superscalar ZSP processor. Various software development strategies will be suggested to take advantage of the instruction pipeline to reduce the processor idle time and maximize the throughput per instruction cycle.

View
 
0 comments
write a comment

Please Login

You will be redirected to the login page

×

Please Login

You will be redirected to the login page

×

Please Login

You will be redirected to the login page