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SEU Hard CMOS Data Latch Designs

Authored on: Oct 31, 2007 by Leonard R. Rockett

Technical Paper / Conference Paper

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The increasing miniaturization of advanced microelectronics drives the magnitude of charge representing information within a circuit to increasingly smaller levels, raising the susceptibility of its corruption by spurious signals. If the interaction of an ion with a semiconductor substrate occurs in close proximity to the data node of a latch circuit, the resultant excess ionization charge collected at the data node may cause the latch to erroneously change state, a single-event upset (SEU).

A number of SEU hardening design techniques have been developed to mitigate the threat of logic upset due to energetic particles. This paper describes the threat posed to Complementary Metal Oxide Semiconductor (CMOS) data latches by energetic ion strikes and examines some commonly used design-hardening approaches.

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