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SERDES Design and Verification Challenges

Posted on: Mar 27, 2017 | Duration: 35 min.
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This 35 minute presentation, led by Jeff Galloway, co-founder and VP of Silicon Creations, highlights the challenges, best practices, and simulation results involved with a 28nm, 4-lane, 250Mb/s to 12.7Gb/s SERDES design using the Analog FastSPICE (AFS) Platform. The AFS Platform is the only circuit simulator that could handle the high speed portions of the design with the required SPICE accuracy, while AFS RF is used to ensure the PLLs meet the required phase noise.

Attendees will learn:
    • SERDES design and verification challenges
    • Complexity of circuit verification at advanced processes
    • Best practices for silicon success

Speaker

Jeff Galloway, Co-Founder, VP, and CTO of Silicon Creations

Jeff is a Co-Founder, VP, and CTO of Silicon Creations. Since founding the company, Jeff has helped start, grow, and manage design centers in Atlanta and Krakow, Poland. He has helped architect PLL and SERDES product lines which now extend to over 100 customers, over 250 chips, and billions of IPs. Before Silicon Creations, Jeff was with HP/Agilent Labs developing high performance SERDES ADCs, and DACs. His interests include analog design, design automation, and silicon test. He holds a B.S. in Electrical Engineering from Georgia Tech and a master’s degree from Stanford University and has 13 US patents.

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