Design Con 2015
Welcome Guest Log In | Register

Totem for IP Validation and SoC Integration Sign-off for Analog, RF, Memory and Mixed-signal Designs

Posted on: Oct 15, 2013 | Duration: 45 minutes
Course | 89 views
0 0
More Info +- Less Info

Totem delivers a comprehensive simulation framework for voltage drop, reliability (EM/ESD) and noise coupling analyses of analog, mixed-signal, and custom circuit designs. It analyzes static and dynamic voltage drop at the IP or full-chip level to verify IP, not only during its design phase, but also during its integration at the SoC-level including consideration for package impact. Totem also performs EM analysis for power/ground and signal nets to ensure compliance against foundry requirements. It enables exhaustive ESD integrity checks verifying an entire chip, I/O-ring, or macro layout for ESD induced failures. Totem’s full-chip analysis includes noise coupling between high-speed digital and sensitive analog circuits through the substrate network. Totem operates on industry-standard data formats and provides a transistor-level layout-based debug and design optimization environment.

View

Please disable any pop-up blockers for proper viewing of this course.

0 comments
write a comment

Please Login

You will be redirected to the login page

×

Please Login

You will be redirected to the login page

×

Please Login

You will be redirected to the login page