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RedHawk for System-aware, Full-chip Power Noise Reliability Sign-off with Impact on Timing

Posted on: Oct 14, 2013 | Duration: 30 minutes
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Cutting edge process technology has taken us to sub-20nm and designs are striving to keep pace with Moore’s Law. At the same time, the smart-mobile evolution is booming. Consumers are demanding new devices rich in functionality but low in power. The result?  More dense and highly sensitive designs with stricter design requirements and a slim margin for error.

RedHawk’s power delivery integrity analysis platform is the industry-standard solution for full-chip power noise and reliability sign-off. Its technologies address the high capacity needs of the latest ultra-large 1B+ node designs, while fully supporting the strict reliability checks for power/signal EM and ESD at the advanced sub-20nm process nodes. RedHawk enables accurate system-aware analysis by supporting chip, package and board co-simulations as well as multi-die/3D-IC analysis. Improved advanced low-power functions allow for analysis and optimization of the latest power-gating technologies, while the Power Jitter Extension (PJX) capabilities enable users to directly analyze the impact of power and/or signal noise on clock jitter. Chip Power Models (CPM) created out of RedHawk help in IC-aware system design for package and board analysis and optimization.

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