Low-Power Design Analysis and Optimization for Mobile and High-Performance Computing Applications
Every new generation of a mobile IC has increased performance, lower power and smaller form factor requirements. Process migration and the shift to 3D-ICs have made these IC designs possible without compromise. To achieve reliable operation of the IC within the context of the system, various aspects of power noise and reliability must be validated:
- Early power analysis and prediction is mandatory to meet demanding power efficiency targets
- Power integrity verification for sub-1V supply voltage levels to ensure performance at specification for all operating modes of the chip
- High-speed low-power I/Os (LPDDRs) must be verified with the impact of core and system noise to meet stringent chip-to-chip communication jitter requirements
- Reliability verification such as EM and ESD should be part of the design process for ICs manufactured using the most advanced process nodes
- Thermal reliability simulations must be performed at the system-level to ensure thermal stability of high-performance die within small hand-held devices
This presentation discusses various aspects of designing Mobile and High-Performance ICs for power and reliability using ANSYS-Apache simulations platforms.