SoC Power Integrity Challenges
Analysis of IC power integrity has drastically changed in the last decade. ICs today must deliver increased performance and functionality above the previous generations while simultaneously lowering power budgets. A comprehensive power integrity and planning platform is required to meet power, performance and cost trade-offs for these ICs. Low-power design styles such as clock-gating and power-gating are commonly used for mobile ICs and these techniques must be rigorously validated by performing mode-aware transient simulations for dynamic power noise. Additionally, as designs migrate to lower supply voltages and advanced technology nodes, dynamic power noise impact becomes more significant due to reduced margins.
This educast will discuss the following topics:
• Challenges in IC power integrity and low-power sign-off
• Simulation requirements for dynamic power noise on ICs using system-aware chip simulations
• Simulation requirements for system co-design using chip-aware system simulations