SoC Power Budgeting Using RTL Power Models
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Designing for low-power IC applications requires a methodology that addresses power budgeting and power delivery integrity, so that design decisions can be made early in the process to avoid over or under design. Since IC designs must deliver increased performance and functionality while meeting reduced power and price targets, it is imperative to adopt a comprehensive RTL2Gate approach that treats power as a design goal from early stage to sign-off.
This Educast will provide useful information regarding how PowerArtist Calibrator and Estimator (PACE) and RTL Power Models (RPM) can improve the accuracy of your RTL power estimation prior to the availability of physical implementation and manage power delivery network integrity early in the process for cost-effective IC and package design decisions.