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Fundamentals of Advanced Real-Time Operating Systems

Posted on: Oct 3, 2011 | Duration: 50 min.
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In this second fundamentals course dedicated to the topic of Real-Time Operating Systems, Embedded Systems Guru, Dr. Dave Stewart, presents some of the more advanced topics of RTOS that even beginners in the field should know. This class begins with a focus on software decomposition of real-time systems using threads, and the model of a real-time thread needed to leverage the scheduler and communication mechanisms of the RTOS. The class continues by presenting various architectures for mapping the real-time threads to the target hardware by leveraging various features of an RTOS.

The importance and the issues of scheduling in a preemptive environment follow. This includes choosing a proper real-time scheduling algorithm, assigning priorities, and dealing with common real-time issues such as race conditions, priority inversion, and reliable inter-thread communication.

For the system implemented using an RTOS, advanced concepts in troubleshooting real-time performance and troubleshooting timing issues are discussed. While many different methods exist, the method presented is primarily based on use of a logic analyzer, to provide a real target- and RTOS-independent view of the timing in the system.

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prabhakar_deosthali Posted Oct 16, 2011

A very detailed and informative presentation on RTOS. May be if some slides are added to give tips on how to simulate various sensors by creating sensor threads instead of connecting to real sensors while debuuging the code , will add some more value. The advantage of writing sensor threads is that you can create all kind of sensor situations ( sensor range, sensor faults etc) which many times is difficult to achieve with the real sensors

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ManjuTD Posted Oct 18, 2011

Good Presentation: Thanks Correction Suggested: RMA rules says period of every thread is a multiple of period of "every" faster thread. The example given in slide tells 10,20,50,100 is harmonic. But 50 is not a multiple of 20, So example should be something like 10,20,40,120 or 10,20,40,80.

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sharps_eng Posted Oct 19, 2011

Striving for 100% utilization is praiseworthy but other work (Spur) suggests that running any system above 70% makes the system tuning unnecessarily fragile; processor bandwidth is still cheap. Sporadic loads are always tricky to handle because of the problems estimating peak loads, and then you must allow sufficient headroom for uncertainty of those estimations. Best reason for using RTOS is speed to market, support and access to working tested code, drivers, middleware and examples. Academic finetuning is interesting but nt a production reality unless your app has a very disciplined, well-defined workload over time. Genuine realtime systems have massive apparent redundancy, can handle worst-case loads and never miss a beat, and can't afford to rely on statistical averaging to come out on target 'most of the time'. Great material here though, I enjoyed it.

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BobC_ Posted Oct 20, 2011

I've had systems that could not be debugged using any of the techniques mentioned in the course, most often when the CPU is heavily loaded and lacks enough spare pins. What I've done in such cases is turn the logic analyzer around: Instead of monitoring chip outputs, monitor the inputs and the master clock. Run the system until the anomaly occurs. Then take the data and create an environment timeline. Use the timeline to create an input script to a software simulator for the chip in use. A cycle-accurate simulator is preferred, but not absolutely required so long as the timing is accurate at the instruction level. First, run the simulator with the timeline to ensure the problem is accurately reproduced. Then run the simulator as the target for your favorite debugger, knowing that when you pause execution you are also pausing the entire world. The power here is not only escaping the real-time environment, but also the repeatability of the test. When a fix is implemented, the EXACT SAME environment input sequence may be used to ensure the fix handles at least that one known example of the issue. I generally create the simulation environment as part of the system design process. It is a great way to sanity-check design decisions, and allows software development to start before the hardware is ready (especially useful for developing hardware bring-up and test code). Many vendors provide cycle-accurate simulators for their embedded chips, and will typically include at least a GDB interface. However, be very careful when MMUs and caches are involved: Some CPU simulators fail to provide accurate MMU and cache simulation. Be sure to validate your simulation environment prior to trusting it. My favorite way to do this is to test against a CPU development board.

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hm Posted Oct 20, 2011

Good presentation. Is it possible to get PDF version of text?

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gerry_smyth Posted Oct 26, 2011

A great presentation; easy to understand even as a beginner for RTOS like myself. The presentation makes me want to learn more and resurrect the logic analyser techniques on hardware that I used a long time ago.

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parinda Posted Nov 9, 2011

what a good presentation, Thank you Dr.Dave, waiting for next presentation on Logic analyzer base debugging on RTOS, actually Logic analyzer is pretty handy tool for testing timing issues.

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cnureddy.b Posted Apr 12, 2012

It is a priceless presentation. Though 49 mins is a short duration but presentation covered most of the RTOS concepts. Hope to see more from Presenter.

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For the system implemented using an RTOS, advanced concepts in troubleshooting real-time performance and troubleshooting timing issues are discussed.

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