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Fundamentals of FPGA-to-ASIC Conversion

Posted on: Mar 30, 2010 | Duration: 35 min.
Course | 926 views
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There are two main reasons why a designer would need to migrate from an FPGA to an ASIC— and many more reasons why that migration could easily go astray. Regardless of whether the designer intends to deploy first with a low-volume FPGA implementation and then move to an ASIC as volume ramps up, or instead if the FPGA was simply intended to prototype an ASIC to check functionality and perform at-speed verification, there are a number of fundamental principles that designers needs to keep in mind.

This course presents those principles and the tools available to act upon them. It starts by summarizing the main differences between FPGAs and ASICs, moves on to discuss the main issues associated with migrating a design between implementation domains, from RTL, synthesis and timing constraints, to test planning, architecture, packaging, pin-outs and interfaces. Finally we consider a number of target ASIC technologies, including standard cell, structured ASICs and conclude with a real-world example using Altera's HardCopy ASICs.

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Patrick Yip Posted Aug 12, 2010

I want to downoad the slides.

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rana ji Posted Feb 9, 2013

Dear Sir Patrick, You are not alone having this wish . When I read your comments I said " me too". But Sorry sir, EETimes guys are super genius. :). In fact these are only available online. I here by also request here that these presentations should be downloadable.

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