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Jim DeLap is an Applications Engineer for Agilent EEsof
EDA. He has worked in the microwave and RF community
for over 13 years, and has a Master's degree from the
University of Virginia. Jim has specialized in
high-frequency and millimeter-wave IC and module design
with further emphasis on EM effects on ICs and
packages.
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Higher levels of integration are the
manufacturer's primary response to the demand for smaller and
lower cost electronic products. While ICs are part of the
solution for this higher circuit density, designers also use
new circuit construction and packaging techniques. A Multi-Chip
Module (MCM) combines multiple chips onto a common substrate
with a single set of inputs and outputs. Multiple chips in the
same module almost always require many more I/O pins;
therefore, Ball Grid Array (BGA) mounting techniques were
developed to accommodate the additional connections.
At frequencies below 1 GHz, the performance of packaging
methods is very well understood. However, many new wireless and
wired communications systems operate at much higher
frequencies, where implementation is not straightforward. At
these microwave or near-microwave frequencies, the
electromagnetic (EM) effects of vias, transmission lines, and
the package-to-board interface are very important and designers
must analyze these effects with appropriate EM tools.
MCM and BGA Technology Overview
MCMs are a type of package where multiple chips share the
same substrate. The common substrate provides multiple layers
for signal and power distribution, ground connections, and
interconnection of common inputs and outputs. A simple example
of a multi-chip module is a RAM SIMM or DIMM commonly used in
computers. With multiple RAM chips mounted on the same board
and using a common set of I/O lines, these modules not only
save board real estate, they also integrate a single function
into one module. Of course, MCMs are not limited to similar
chips; you can put different chips that make up an entire
functional block of a subsystem into an MCM.
The increased number of connections needed for multiple
chips requires new methods of attachment. Traditional IC
packaging has a single chip bonded to a lead frame with pins
along the outer edge. As more pins were needed, it became
impractical to route signals to the outer edge of the IC.
Engineers originally came up with the PGA (Pin Grid Array), a
rectangular array of vertical pins which allowed a much higher
density of interconnects than standard SIMMs, DIMMs, DIPs, and
similar chip packages. However, with higher frequency clock
signals, the pins present too much inductance to be useful. The
BGA was then developed, using solder reflow technology to
attach all the connections in a single operation. The balls
also provide a means of matching the thermal coefficients of
expansion between the MCM substrate material (typically
ceramic) and the board.
Simulation Issues for MCM Circuits
You can characterize MCM packages as sheets of dielectric
material with circuit traces and vias routed on, between, and
through the dielectrics. This layered construction makes it
possible for planar electromagnetic (EM) simulators to perform
the analysis, instead of the much more complicated and slower
three-dimensional EM simulator.
Not all of the EM tools on the market can accurately predict
the complete interaction between traces, vias, and
interconnects. Many of them simply analyze traces using a
two-dimensional cross-section solver that analyzes the
dielectric layers and calculates transmission line
characteristics along a critical network. This method typically
uses a quasi-static approximation of Maxwell's equations, which
is limited to lower frequencies where the physical size of the
circuit is small compared to the wavelength of the circuit's
operation.
The most common method for complete analysis of larger
circuits, and at higher frequencies, is the Method of Moments
(MOM). This type of EM simulation is often referred to as 2.5D,
with the extra half dimension indicating that the simulator can
calculate currents in the z-direction (usually vias) as well as
the x- and y-directions. Basically, a Method of Moments
simulator includes both the dielectric layer stackup and the
physical layout of the traces. The dielectric stackup is how
the various dielectric layers are arranged, with their
respective permittivities, to simulate a cross section of the
circuit or package. Adding the metallization layers to the
substrate structure, including metal conductivity and thickness
parameters, completes the circuit definition.
You have to either draw or import the physical layout to
describe the circuit's metallization. The layout of the traces
may be drawn using a simulator's layout tool, or they may use
the simulation tool's capability to import from DXF, GDSII, and
other common drawing formats. In some analysis tools, there is
also a step to map the polygons that describe the trace
metallization to the physical location of the metal patterns in
the substrate stackup.
Once you define the simulation problem with the physical
structure and material characteristics, the layout can be
discretized (divided into small sections) for calculation of
currents and S-parameters. Since these tools implement a
full-wave solution to Maxwell's equations, they include
calculations for radiation effects, dielectric loss, and
metallization loss, which are crucial to the high-frequency
circuit simulation using these packages.
As noted earlier, there are other tools that incorporate the
full three-dimensional aspect of the problem by breaking up the
volume of the model into 3D elements, applying boundary
conditions, and solving Maxwell's equations for the electric
field. These methods are time consuming, both for the creation
of the model and in computation time. For most applications, a
planar MOM solver is more than adequate. In the future, when
MCM and BGA technology is used for even high
frequencies"millimeter wave and up"you may need 3D solvers, but
that point has not yet been reached.
MCM Simulation Examples
To simulate MCMs and BGAs, the most important tasks are the
definition of the dielectric stackup and the description of the
three-dimensional structure in two-dimensional layers. The
examples shown in this article are simulated using DuPont Low
Temperature Co-fired Ceramic (LTCC) material systems, unless
otherwise noted.
The ceramic is the standard Green Tape 951,
and the simulated metal systems are Au 5731.
The first example covers a problem area in MCMs utilizing
LTCC materials: poor adhesion between metal and ceramic. Some
ceramic layers do not completely bond to the metal layers.
Although there is progress toward solving this problem, some
vendors of LTCC systems recommend (or require) the use of
meshed, or grid type, ground and power planes to allow contact
between adjacent ceramic layers for improved bonding. This
means that the metal plane separating two ceramic layers cannot
be solid. DuPont typically recommends 70 percent maximum
coverage.
However, the use of mesh ground planes presents several
problems for high-frequency applications. The first is simply
increased resistive losses for the ground currents when the
layer is used as an RF ground. This obviously results in higher
losses. The second problem, not as obvious, is related to the
finite size of the mesh openings and the period at which they
repeat. These physical factors can cause the grid to act as a
filter, referred to as a photonic bandgap structure.
From Reference and the parameters of this example, the
frequency range of this phenomenon is around 50 GHz, which you
can generally neglect. Simulations of solid and meshed ground
planes are shown in Figure 1 and Figure 2, with a graph comparing the results shown in
Figure 3. The 2D layout of the mesh ground plane is
shown in Figure 4 to illustrate how structures are drawn
in a layout environment.
Figure 3: A comparison of the S21 (loss) simulation
results in a microstrip line with solid and mesh ground
planes
Figure 4: Layout of the mesh ground plane in two
dimensions, showing the position of the microstrip line
relative to the grid structure
The dielectric stackup for this simple example consists of
air for the upper boundary of the line, the strip of
metallization, and the ceramic-substrate dielectric. The bottom
boundary is the ground plane defined earlier in this article.
All the MCM examples in this article are variations of this
definition.
The ground reference for the simulation stimulus requires
special attention. First, if a solid ground plane is used, the
stackup description defines the plane and you calculate the
substrate functions with the assumption that the ground
reference is an infinite, homogeneous ground plane. However, in
the case of the mesh ground plane, you need an alternative
ground reference, since the effects of the mesh "ground" must
be part of the analysis. In most EM simulators, if a ground is
not explicitly defined, the reference is assumed to be a sphere
of infinite radius. The simulator used in these examples
includes a ground reference port that allows an explicit
definition of the ground state. This technique is also used in
the next example, where the ground plane separates one mode of
propagation from another defining the transition from
microstrip to stripline.
The routing of transmission lines under or around active
devices is the subject of the next example. The structure we
will analyze begins with a microstrip line on the top
dielectric layer, followed by a plated-through via hole that
forms the transition to a stripline on a buried layer, then
back up to microstrip. A 3D view of the structure is shown in
Figure 5 and the S-parameter simulation results are
shown in Figure 6.
Figure 6: S21 (loss) simulation results for the
structure pictured in Figure 5
Where the vias transition through a solid ground plane,
there must be openings ("anti-pads") to prevent shorting to
ground. Design guidelines for the substrate material will limit
the size of these via hole openings, which are a minimum of 50
mils in the DuPont system. This guideline accounts for the
shrinkage of the dielectric and metal tapes during the firing
process, which is 12.7% in the x-y plane for the 951 system. If
the openings are too small, there will not be adequate
clearance for the via holes.
Designers must also consider the number of layers through
which the vias travel. If there are vias that extend all the
way through the substrate and are attached to signal lines, we
must be very careful that they do not act like open- or short-circuit stubs. This is especially true for very thick
substrates with many layers. Fortunately, the LTCC processes
have the flexibility to produce vias that extend only through
the necessary layers. This is not always the case with
conventional PCB processes.
One advantage of the MCM methodology and LTCC implementation
is the ability to incorporate passive components, which require
additional structures for simulation using these planar EM
simulators. The next two examples show simulations of a 3D
inductor and a parallel-plate capacitor. The inductor is
created in three dimensions, using the multi-layer media to
reduce the x-y periphery that a single-layer or spiral inductor
would need for the same inductance. Figure 7 shows the inductor model while Figure 8
shows the inductance simulation results.
Figure 8: Simulation results for the inductor shown
in Figure 7
For a capacitor, the plates are typically constructed as
metal areas on adjacent layers with the ceramic dielectric
layer between them. You can design integral capacitors using
this technique for device matching, AC coupling, or even
lumped-element filters. The capacitor structure and simulation
results are shown in Figure 9 and Figure 10 respectively.
Figure 10: Simulation results for the capacitor
shown in Figure 9
The advantages of using MCMs with LTCC or other substrate
media are clear. You can easily integrate multiple chips on the
surface of the substrate, with signal routing and power/ground
distribution that uses buried layers. These MCMs can also
include passive elements for attenuation, matching or tuning.
However, designers must remember that unexpected behavior at
microwave frequencies is likely unless they accurately analyze
these circuits using a planar electromagnetic simulator.
Simulation of BGA Connections
In many cases, the BGA attachment method is used for MCM
connection to the printed circuit board. The ball attachment
method can vary, with balls usually soldered or brazed onto the
package. The balls can also vary in size and pitch, but the
smaller the ball, the higher the frequency at which the package
can operate.
For BGA simulation, we can assume that a solder fillet will
create a cylinder when the package is mounted onto a board.
Since most EM tools can simulate vias, we can approximate the
ball interconnection with a cylindrical shaped via. For RF
signals, the high-frequency signal connection can be surrounded
with ground balls. This is one technique to minimize radiation
and confine electric currents, since it creates a
pseudo-coaxial transition.
An example of a typical microwave BGA is shown in Figure 11. This example uses an alumina package from
Micro Substrate Corporation (Model 1MSC633Z). The company
designed the package, which contains eight DC ports, to operate
up to 31.5 GHz for the input and output transitions.
Understanding the performance of the BGA interconnect is the
most important aspect of this package at high frequencies,
because the path length from the die to the mounting substrate
adds inductance that can ruin the frequency response of a
circuit mounted in the package. For simplicity, the simulation
only examines the RF transition. The simulation results are
shown in Figure 12, which also includes a comparison
with measured performance.
Figure 12: A comparison of simulated and measured
insertion loss of a BGA soldered connection
Simulating Bond-Wire Connections
The final example shows how these tools can also be used to
simulate bond wires to chips mounted on the top layer of the
substrate. A 3D view of the example is shown in Figure 13. The figure shows a 96-pin BGA package with
an IC mounted on top. For simulation, two layers above the
substrate define the dielectric of the area surrounding the IC
and the area surrounding the bond wires. The bond wires are
simulated with a vertical via section from the IC pad, a
horizontal trace to a point above the bond pad, and a vertical
via down to the bond pad. While not precisely modeling the
three-dimensional wire loop characteristics, this method of
simulating wire bonds is a good approximation to about 20 GHz.
The simulation results for line loss and crosstalk between two
adjacent pins are shown in Figure 14.
Figure 14: Results of the simulation for crosstalk
between adjacent connections and insertion loss of a bond-wire
connection
Summary
New computing and communication products continue to have
increased packaging densities and higher frequencies of
operation. To assure that a design will perform as designed, it
is essential that designers consider electromagnetic effects.
The examples presented in this article show how planar EM
simulation tools can provide valid results without requiring
the intensive computations and effort that full
three-dimensional solvers require.
The simulations in this paper were performed using the
Advanced Design System 2001's 2.5D Method of Moments solver,
Momentum from Agilent EEsof EDA. For more information on BGA
design or to download the ADS 2001 design file used in this
article, visit www.agilent.com/eesof-eda.
Acknowledgements
The author would like to thank Bob Griffin from Micro
Substrates Corporation along with Joe Civello and Chris
Mueth from Agilent Technologies.
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