CMOS VCSEL Driver Design at 1Gbits/s for High-Speed Optical Communication Applications

With lithography techniques rapidly approaching 0.10 µm and smaller, the combination of small device dimensions and high-speed data rates causes many problems for IC designers working in this high-speed/high-frequency arena. To illustrate these issues, this article will demonstrate the modeling and simulation of substrate and package effects for a 1 Gbit/s laser driver optical electronic integrated circuit (OEIC) design. The driver uses a 0.13-µm CMOS process, which drives a vertical cavity surface-emitting laser (VCSEL). The design was done using the High Frequency SPICE and Convolution simulation engines in Agilent Eesof's ADS 2001 tool suite.

The silicon CMOS-process stack-up is modeled using ADS' multi-layer library substrate definitions. Multi-layer vias, multi-layer coupled lines and additional distributed transmission line effects are added by referencing the modeled CMOS process stack-up conditions prior to layout and parasitic extraction utility engagement. Results are given for both a traditional analog design approach and this method, which adds semiconductor substrate and transmission line multi-layer effects into the design. The article shows how a high speed analog IC designer may incorporate substrate effects at each level—IC, package and board—without requiring any special interface between CAE packages and external data files.

High-Speed IC Design Issues
Designing high-speed analog and digital circuits for the data-communication industry is an extremely difficult task. Today, the task is especially difficult as data rates explode well beyond 1 to 40 Gbits/s (OC-768). Integrated circuits, which provide the optical-to-electronic transition for these network systems, are the most difficult components to design in a fiber-optic transceiver. These optical electronic ICs (OEICs) include the laser driver, generating the electrical current to modulate the laser, and the transimpedance amplifier, which receives a very small current from a photodiode and must amplify it with minimal noise effects.

At higher data rates, OEIC design techniques must include more effects than those typically incorporated into a more traditional custom analog IC methodology. These traditional designs model the IC within a Spice engine, run a logic vs. schematic (LVS) comparison, then add the extracted view of the parasitics (such as resistive transmission-line losses and capacitive coupling to ground) from a parasitic extraction utility engaged within a layout tool. With Gbits/s bit-stream data rates, the traditional simulation methods (Spice) and analog/mixed-signal modeling techniques (lumped element, Verilog/VHDL, and Verilog-A) are decreasing in accuracy. Even at the data rate of the OC-48 standard, design techniques need to include frequency-domain parasitic effects. At high speeds, these OEIC circuits essentially become full-custom high-speed ASICs. The parasitic effects are even more pronounced at the increased data rates for OC-192 and OC-768 applications. As a designer, you have to be able to effectively design with both time-domain and frequency-domain perspectives to adequately account for parasitics while meeting the specification requirements for all OC standards.

A designer should account for all high-speed effects during product development, especially if the goal is to achieve first-pass working-prototype success. The challenge is to accurately predict the high-speed digital-signal parasitics for these optical systems. These parasitics are evaluated in the form of jitter, crosstalk, skew and groundbounce, which are generated by series inductance on the datapath, substrate coupling effects at the bulk-surface level, package structure, and board-generated effects. During OEIC design, you need to account for each of these effects as they occur along the signal path.

Parasitic effects result in a degraded eye pattern and added jitter. These parasitics include semiconductor substrate effects of the process technology in which the chip will be processed, IC transmission-line effects, chip-to-package effects (bond pads and bond wires), package effects of the leadframe, package-to-board interaction parasitics, and board-level high-speed transmission-line effects. The type of package (if any) a particular application uses really doesn't matter. These chips may use SOIC, BGA, or even flip-chip packages with gold solder. Different packaging options will have varying degrees of parasitic inductance. What matters most is that the parasitic inductance of the packaging needs to be included during the initial stages of the design.

The design in this article was simulated using time- and frequency-domain simulators, incorporating the parasitic effects of the package, bond wires, bond pads, and substrate effects. The IC designer should do this simulation before using any parasitic-extraction utilities. By designing these parasitic effects into the IC, this design methodology increases the chances for first-pass success, can save hundreds of thousands of dollars in foundry and reticle costs, and may take months of prototype-fabrication time off the product development cycle.

Successful OEIC design requires the following simulator functions and features:

• Transient simulation: A robust time-domain simulation engine with very good convergence capability is necessary.
  
  
• Convolution capability that handles S-parameters and distributed models: This capability allows the simulator to handle frequency-domain elements, S-parameters, and parasitic effects during time-domain simulation without having to create lumped-element RLGC-based models. Convolution allows a designer to work in time and frequency domains depending on the design specification.
  
  
• Multi-layer models for vias, crossovers, coupled lines, and transmission lines.
  
  
• Multi-layer substrate model: Lets the designer model process stack-up.
  
  
• Distributed transmission line models and the ability to handle these models.
  
  
• The ability to generate RLGC networks and save them in a file: Lets the designer compare results to those results obtained using parasitic-extraction utility tools.
  
  
• Planar 2.5D electromagnetic simulation capability.

VCSEL Driver Circuitry Figure 1 shows the typical circuit topology used by a standard analog IC design methodology, which incorporates only the bond pad and its effects into the initial design. In the initial design, these effects were modeled by a 45-fF capacitor to ground for the bond pad, in series with a 1 nH inductor to the package leadframe, at each port. This lumped-element model represents how an IC designer would include these effects in a SPICE simulator. Figure 2 shows the topology of the voltage reference circuit for the VCSEL driver circuitry for improved temperature performance.

This CMOS VCSEL driver is capable of having an adjustable current drive between 0 and 45 mA, obtained by varying two resistive loads. The modulation current of the laser driver can also be adjusted over the same 0 to 45-mA range. In addition, the simulation used a VCSEL model to represent the parasitic capacitance and resistance of the VCSEL itself (Figure 3).

Figure 3:  VCSEL model with parasitic capacitance

The CMOS VCSEL laser-driver design is based on a differential pair of transistors at the input. The input current pulse drives one gate while the other gate is biased at a DC reference level set by three transistors in a voltage-divider configuration. The tail current through the first-stage differential pair equals the total modulation current. The voltage at the gate of the DC-biased differential pair is designed to be at the middle of V_in (peak-to-peak). With the simulated results, you will see the eye pattern amplitude drop with the addition of package effects. In addition, V_in(p-p) changes with the loading/lead effects of the package.

A cascode current source biases the output-drive transistor that provides the DC component used to pre-bias the VCSEL. The cascode current source topology was chosen because the current mirror assures that a very high output resistance does not load the CMOS VCSEL driver and, therefore, does not have much effect on the circuit's high-speed performance. During the circuit's initial design, 1Gbits/s was chosen as the starting circuit speed specification.

Including High Speed Effects
First, by modeling the substrate process stack-up conditions, which were determined from the silicon CMOS process for the circuit, the substrate effects for the 0.13 µm CMOS process were added. Since the process had eight copper metal layers, the eight-layer multi-layer library substrate definition was chosen to model the substrate and pass the these effects to the quasi-static field solver within the multi-layer library components. Coupling between metal layers at various points on the ground and power-supply rails were added to simulate crosstalk and field effects that would occur as the circuitry modulated the current from the supply rail through the ground rail. 0.25 µm cylindrical vias were added on the data I/O path between the Metal 1 and Metal 6 layers within the circuit. It is very important to account for these vias before any parasitic extraction is done because of the amount of series inductance they add between the different metalization layers. In addition, multi-layer-transmission substrate-coupling effects were added between each node of the original VCSEL driver schematic.

The multi-layer transmission lines added were 10 µm long by 5 µm wide. These dimensions are based upon traditional analog IC-layout techniques for custom designs. Substrate effects of the process stack-up were then defined to include skin effects and various dispersion effects, which are referenced from the substrate definition statement. Finally, the proper heights of the various layers were added, along with dielectric constants, loss tangents, and conductivity of the various layers (for example, whether a layer is a dielectric material or a conductor). Figure 4 shows a view of all of these substrate components added to the original VCSEL driver circuit. The addition of these substrate components was not done to the static voltage-referencing circuit since it is, obviously, out of the signal path. Figure 5 shows the substrate definition component used to model the eight copper-layer bulk-silicon CMOS substrate.

Figure 5:  Eight-metal-layer substrate definition symbol. Metal-i represents metallization-layer parameters—thickness, conductivity, and type (conductor, power, or ground). Dielectric-i represents dielectric-layer parameters—permittivity, layer height, and loss tangent

The design was started with the intent to use an RF BGA package to encapsulate the IC. The package was modeled and simulated using the Planar 2.5D EM simulator integrated into ADS. The package was analyzed up to 10 GHz and the results from the field analysis were added to the substrate effects during the time-domain simulations of the VCSEL driver circuit at 1Gbits/s.

Figure 6 shows a visual representation of the package. Figure 7 shows data from the EM simulation on the data-input lead while looking at its loss or attenuation over frequency up to 10 GHz. The crosstalk is calculated from the data-input lead to the next adjacent pin on the bottom of the package. The graph also shows how coupling or crosstalk increases with frequency or increasing data rate.

Figure 6:  Modeling a BGA package

Figure 7:  BGA package simulation results for Data Input lead

The data for the package (which resides in S-parameter format) was added to the ports of the VCSEL driver circuit and connected to the proper pins, with the data pins being orthogonal to the supply-rail and the ground leads. The orthogonality of the leads decreases the effects of the EM fields as the modulation drive current of the circuit approaches 45 mA. Crosstalk for all leads was modeled during EM simulation. Once the data is fed into the time-domain simulation, the S-parameter data is converted using the convolution simulator. Having convolution capability means that the package does not require a lumped-element RLGC model generated in Spice syntax in order to be simulated with the VCSEL driver circuit. This feature gives the designer the opportunity to skip the process of creating a lumped-element model of the package, as well as additional opportunity to avoid inaccurate Spice models generated from the conversion of the frequency-domain package model. One could still create a lumped-element RLGC network for each of the package leads, but using the frequency-domain data in a time-domain Spice simulation saves time and reduces errors.

Figure 8 shows the results of four simulations run at 1 Gbit/s on the laser driver and voltage-referencing circuit using the VCSEL model as the load. The four types of simulations were:

1. A standard IC design simulation with no parasitic effects other than lumped-element bond wire and bond pad models
   
   
2. Adding the substrate effects (transmission line losses, coupling, and vias) while referencing the process stack-up definition statement
   
   
3. Adding the package-model effects with the standard IC design circuit
   
   
4. Adding both the package-model and substrate effects.

Figure 8:  VCSEL driver simulation results at 1Gbits/s

These four graphs show that the initial circuit was designed for an output-current swing (single ended) of about 5 mA with the current state of the two load resistors. At 1 Gbits/s, the substrate coupling, crosstalk, and via effects are small but are still visible, even at a 1 Gbits/s bit-stream, so that these effects should be taken into account. The single largest effect on the eye-current degradation is from the package. The swing of the eye after package effects are introduced into the simulation shows a current-swing reduction of about 1 mA. This is almost 20 percent of the current swing of the initial design. Later simulations, run at 2.5 Gbits/s and 10 Gbits/s, showed much more dramatic degradation of the output modulated current, caused by the increased parasitic effects of the data rate.

Conclusion
Device sizes are rapidly approaching 0.10 µm as lithography techniques and vacuum-physics technology are refined. At the same time, the data rates of communication systems is increasing beyond 1 Gbits/s, to 40 Gbits/s. With dimensions this small and speeds this high, circuit designers must think about the substrate, package, and other planar effects which will degrade a circuit's performance. The VCSEL design approach described in this article allows the OEIC designer to choose how to incorporate those high-speed parasitic effects, either in the time domain or frequency domain. For high-speed analog custom-IC circuits, the IC designer will need to incorporate frequency-dependent effects into the time-domain-based simulations (modulated current of the eye, jitter, or BER). However, inclusion of these effects should be done only after modeling particular parasitics using frequency-domain analysis techniques.

For this design of a silicon CMOS-based VCSEL driver circuit, traditional analog IC-design methodologies are incorporated into a MMIC type of circuit-design approach, incorporating many of the parasitic effects into the simulation while simultaneously engaging the high-frequency Spice time-domain analysis engine. As a final check, a designer can run the extracted netlist from the parasitic-extraction utility to verify circuit performance with the modeled substrate effects for final verification before tape-out and creation of the GDSII file. From a high-speed designer's perspective, there are tremendous benefits for simulating high-speed and high-frequency effects in either the frequency domain or time domain without being forced to use one or the other.

References

About the Author Russ Kramer has been with Agilent EEsof since 1998, specializing in IC business development. He received his Bachelor's and Master's Degrees from Pennsylvania State University in 1987 and 1989 respectively and an MBA from Loyola College of Maryland in 2001. His interests and experience are in semiconductor processing, and high frequency/high speed IC/MMIC design on III-, V-, and IV-based substrates. Russ has design experience using GaAs, SOI CMOS, bipolar, and BiCMOS processes. He is a member of Eta Kappa Nu and Tau Beta Pi, and a senior member of the IEEE.