But PCI Express isn't the only high-speed interconnect trying to rev up I/O (Table 1). Others, such as RapidIO and HyperTransport, provide some overlapping capabilities and boast of advantages over PCI Express in some cases. HyperTransport, for example, is already well established as a processor interconnect for AMD and MIPS processors. RapidIO claims to be better suited than PCI Express for high-performance embedded systems. Most experts say that some systems are likely to have two, or even all three of these interconnect technologies working together.

To put the various high-speed interconnects in perspective, first consider just what PCI Express is—a serial, point-to-point link, not a parallel, multidrop bus as PCI is. Parallel buses such as PCI and the higher-speed PCI-X have limitations (Figure 1). There's crosstalk between parallel signal lines, and there's signal skew: Data bits arriving via separate lines are out of sync unless all the signal lines are precisely the same length. As a result, PCI's bandwidth has just about maxed out. It's difficult to scale the clock frequency up or the voltage down, and virtually no more improvements are possible in signal routing through FR4 circuit-board material.

Figure 1:  Limitations of the PCI bus and other parallel, multidrop buses

With its serial implementation, PCI Express gets around PCI and PCI-X bandwidth limits (Figure 2). With PCI Express data bits traveling serially, signal skew between parallel lines is no longer an issue. PCI Express also minimizes the crosstalk problem by using low-voltage differential signaling (LVDS) instead of single-ended signaling. Consequently, data can move on a basic four-wire PCI Express link at 2.5 Gbits/sec in each direction simultaneously. After accounting for overhead, the resulting bandwidth is about 400 Mbytes/sec—considerably more bandwidth than PCI and far more bandwidth per pin (Figure 3).

Figure 2:  Basic four-wire PCI Express interconnect

Figure 3:  Scalable PCI Express bandwidth

PCI Express also consumes minimal space on a circuit board. By some estimates, a PC motherboard using PCI Express can be 50% smaller than a motherboard using a traditional PCI bus. If that seems implausible, first consider that you need a lot of traces for a 32-bit-wide or a 64-bit-wide bus. Also, parallel bus traces on a motherboard usually can't go straight from one point to another. To minimize signal skew, they must be precisely the same length, which means they often take serpentine paths, meandering over a substantial part of the board. PCI Express, with as few as four traces, can go point-to-point.

Probably the greatest appeal of PCI Express, however, is its scalability. With the addition of more "lanes" via extra wires, PCI Express bandwidth increases linearly, up to 16 Gbytes/sec for an x32 link of 128 traces. Future improvements in silicon will likely provide even more scaling via increased clock rates. As a result, applications incorporating PCI Express have plenty of room to increase performance capabilities. "It's tremendously impressive how much PCI has been scaled," says Larry Chisvin, vice president of marketing for chipmaker PLX Technology, "but you're pressing the limits of what you can do with any parallel bus. With PCI Express, you're starting new, and you have nothing but headroom."

With its many possible configurations, PCI Express will find other uses, too. In an x1 configuration, for example, it will serve as an interface to PCI ExpressCards, an upcoming, smaller counterpart to PCMCIA cards. For other applications both in PCs and elsewhere, says PLX's Chisvin, x4 and x8 seem to be the sweet spot, because they provide a lot of bandwidth at some reasonable size.

Although PCI Express is suited for use in many markets and applications, its natural fit is in the PC. The technology originated at Intel, after all, and it's software compatible with the PCI bus, which is pervasive in PCs. PCI Express was also designed to cost as little as, or less than, the PCI bus to implement, although the cost will likely be somewhat higher until high-volume, commodity parts become available. Also, PCI Express's high bandwidth makes it useful as an attachment point for other, existing interconnects, such as USB, 1394b, InfiniBand, and Ethernet.

PCs need more than bandwidth to handle today's multimedia requirements, however, so PCI Express includes features to meet multimedia quality-of-service (QOS) needs. It provides isochrony, for example, so that data packets can move at a time-constant rate to prevent audio and video dropouts. It also allows devices to request and receive a defined bandwidth allocation that they can depend on.

In general, competition among PCI Express, HyperTransport, and RapidIO will depend on whether the use is for on-board chip-to-chip interconnect or something more. "If you're talking pure chip-to-chip interconnect," says PCI-SIG chairman Tony Pierce, "they all compete in that space." Dan Bouvier, chairman of the RapidIO Trade Association (RTA) concurs. "If we're talking about local chip connectivity," he says, "they're on top of each other."

The situation changes, however, for other uses. For example, both HyperTransport and the original version of RapidIO use many more signal lines than PCI Express for comparable bandwidth, and that makes them less suitable than PCI Express for backplane use. An upcoming Serial RapidIO, using fewer lines, will change that situation, however. PCI-SIG views Serial RapidIO as a competitor to PCI Express, whereas it sees HyperTransport and the original RapidIO—both of which it deems chip-to-chip interconnects and less of a "system interconnect" than PCI Express—as complementary.

In many cases, the choice of a processor will determine the interconnect technology used. Because of PCI Express's Intel origins, it's closely aligned with the x86 architecture. Similarly, HyperTransport originated at AMD and is associated with AMD processors and MIPS-based communications chips. RapidIO, originally from Motorola, has strong connections with the PowerPC processors of Motorola and IBM. PCI Express and HyperTransport are both software compatible with the PCI bus, whereas RapidIO is not.

Application area will also influence, if not dictate, choice of interconnect technology. PCI Express has an advantage in the PC world, of course, and HyperTransport is strong in networks and servers. RapidIO was designed specifically for high-performance embedded systems and would seem to have an edge there. However, in existing systems of any kind that need performance upgrades, one interconnect technology won't necessarily replace another, at least anytime soon. Instead, newly available and soon-to-be-available bridge chips will allow two or more interconnect technologies to coexist. PLX Technology and many other companies are making chips that will bridge just about any interconnect technology to any other.

In high-performance embedded systems, such as communications infrastructure equipment, performance features give RapidIO an advantage over other interconnects. It has peer-to-peer communication among multiple processors, for example, which comm equipment and other high-performance equipment often need. This contrasts with typical PC usage in which peripherals communicate with a common host processor through shared memory. "The focus of PCI Express and HyperTransport is to connect peripherals to a host," says RTA's Bouvier. "RapidIO addresses system connectivity of peer computing elements."

But not everyone grants RapidIO an easy victory in the high-performance embedded space. "We see PCI Express in imaging, medical, and factory automation," says PLX's Chislin. "We believe that PCI Express will penetrate every market. It will definitely penetrate markets that today PCI and PCI-X penetrate. Then, because of its serial nature and high bandwidth and extra features for quality of service, it will penetrate places that PCI currently doesn't. Having a serial connection that is completely software compatible with PCI-X is very attractive."

RapidIO proponents acknowledge, too, that PCI Express can work adequately in some high-performance environments. "There are certain applications where PCI Express and its capabilities may be adequate," says RTA's Bouvier. And although RapidIO claims that features such as low latency and high determinism give it superiority in embedded systems, PCI-SIG's Pierce counters that latency and determinism often depend less on the technology used than on the components used to implement the technology. For example, says Pierce, "If you have switches in the fabric, they can have tremendously different amounts of buffering in them."

RapidIO's Bouvier doesn't buy PCI Express's supposed cost advantages, however. It's a common misperception, he says, that PC technology, because of its commodity nature, can reduce costs when used in embedded systems. "If you open embedded equipment and look under the hood," Bouvier claims, "you'll find almost zero component crossover from the PC base." PCI is actually a small part of the embedded space, according to Bouvier, despite the high visibility of the PCI Manufacturers' Group (PICMG). A large number of embedded players use PCI, Bouvier says, but it makes up a small volume of embedded components.

Selection of an interconnect for high-speed embedded systems is further complicated by the fact that all the interconnect technologies are being expanded beyond their initial purposes. RapidIO's serial version, for example, puts it in competition with PCI Express for backplane use. Not to be outdone, a cable version of PCI Express, now in development, will make PCI Express competitive with RapidIO for short board-to-board and box-to-box connections. As a result of these changes and others, interconnects' technical capabilities overlap much more than they originally did. To complicate matters still more, planners of various interconnect extensions are racing to be first to market, knowing that design wins are often based not on technical superiority, but on squatter's rights.

In the end, we're likely to see high-speed interconnects working together in many cases. PCI-SIG's Pierce, for example, expects to see systems with HyperTransport in them supplying many different aspects of PCI Express technology at the card slot. "Where there's a bridge [from HyperTransport] to PCI or PCI-X today," he says, "there will be a bridge to PCI Express."

We will also see different high-speed interconnects working separately from each other, each filling a performance niche that no other interconnect fills. As RapidIO's Bouvier says, "There will be not just one winner in this perceived race, but multiple interconnects optimized in different ways."

And, without a doubt, we will still have the original PCI bus and its higher-speed descendent, PCI-X. The planning for PCI Express included provision for coexistence with PCI and PCI-X, and as plentiful as these buses are, they won't be going away for a long time. Like the ISA bus before it, PCI will live on long after its obsolescence.