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Ralph Zak
Adaptive Silicon
TechOnline
Using embedded programmable logic can reduce the time spent on
the verification of large system chips. With chips becoming
increasing large and complex, nearly as much time is taken to
verify a chip as to design it. Now, a designer can put a
programmable-logic IP core on a multi-million-gate design. By
placing the high risk design blocks in a programmable-logic core
embedded in an SoC, the verification engineer is able to tune his
silicon and make changes without having to spend months either
simulating corner-case conditions or building and debugging FPGA
prototypes.
Defining the Problem
Designers are currently working on many complex integrated
circuits of more than a million gates in complexity. Typically,
system chips are complex devices with embedded
processors—DSPs, microprocessors or
microcontrollers—along with embedded software and other major
functions that add an application-specific personality to the
devices. Such designs are not new. The requirements to reduce power
consumption, size, and weight of wireless handsets drove the major
cell phone manufacturers to embed DSPs, microcontrollers, vocoders,
and other blocks into individual ASICs. Similarly complex ICs can
be found in other portable devices, such as video cameras and
digital cameras. The drivers for these products are similar—a
common need to reduce power, size, and weight. Typical complexities
of the devices designed in these application markets over the past
few years were 1 million gates or less, but current devices under
development are in the 1-3 million-gate range.
In communications, bandwidth is the key driver for increasingly
complex system chips. In these applications, 2-3 million-gate
devices are common. The network processor is a term that has
evolved to describe a new class of SoC networking devices. The
author has encountered customers who are planning systems with
devices in excess of 10 million gates. Other customers have planned
complex multiprocessor systems in which a single system may include
up to ten circuit boards, each with ten ASIC devices over a million
gates in complexity, with individual chips having up to
five-million gates. In such systems, the majority of such devices
are for control within the system to optimize performance and
broker conflicts between the processor and different datapath
functions. The opportunity as semiconductor geometries move to 0.13
microns and below is to begin aggregating these complex,
control-oriented devices with the processors in ever more complex
system chips.
While much of the functionality built into system chips is
generally comparable in complexity to systems comprising multiple
components, the risk of designing a single device is greater. This
increased risk arises from many sources, including:
- The use of silicon IP from companies for major building blocks
that are much less proven than traditional ASSPs used in
systems
- An order of magnitude increase in control-logic complexity from
the use of multiple processors and parallel processing of many
functions
- A lack of design debug visibility into system chips versus
traditional system-level lab debugging tools
- The difficulty and expense of potential field upgrades.
Embedding programmable logic into these very complex devices of
one to many millions of gates can greatly minimize the project
risks. Embedded programmable logic adds other benefits, such as
easy field upgrades and the ability to leverage a single
development effort and prototype chip-debug effort across multiple
designs in a product family. Many system-design teams have relied
on extensive use of large farms of compute servers for simulation
and multi-million-dollar chip-emulation systems for verification of
their products to minimize the risk that they will have to go
through multiple prototype chip cycles. Such cycles can add months
to project schedules and millions of dollars to project budgets.
Ironically, most of the design risk is typically constrained to a
few major blocks of the design.
Advantages of Embedding Programmable
Logic
If these blocks could be implemented in design-flexible
programmable logic, this would allow design teams to tape out their
chips earlier and get a head start on debugging, without the fear
of having to build multiple prototypes. The first prototypes could,
in fact, be the production chips. Any functional errors in the
design of the critical blocks in programmable logic can be quickly
changed and reprogrammed, bypassing the complexities of a new
layout, achieving timing closure, photomask making, and going
through the fabrication process again.
Embedding programmable logic has other benefits as well. Not
only can you minimize initial design risk, but once programmable
logic is within the chip, you can easily implement upgrades to
accommodate various scenarios, much like downloading new software
device drivers to your computer. When used to implement emerging or
changing standards, as is the typical case in networking and
wireless communications, the design specifications and development
effort can proceed if blocks of the design likely to be affected
are targeted to programmable logic. By taking such an architectural
approach to the design, a company can obtain a large time-to-market
advantage over competition that chooses to wait until standards are
firm, which in some cases can take years. The alternative, choosing
to proceed without embedded programmable logic, can lead to the
inevitable redesign cycle with every change as the standards firm
up.
As product life cycles shrink, more and more companies are
engaging in parallel product-development programs. Development
cycles can still often stretch to 18 months or more from
architectural development to production shipments. Often products
within a family share many similarities. By embedding programmable
logic within ASICs or ASSPs, you can achieve product
differentiation by simply programming in the differentiating
product features within the various members of a product family. By
designing these ASICs with this intent, the same chips can be used
in multiple products, avoiding the multiple development efforts,
verification cycles, and prototype chip-fabrication cycles of
completely different chips.
From a chip timing and performance standpoint, clock rates
continue to go up quickly, and interconnect delay becomes more
critical. Characterization of block-level timing is more and more
important as timing analysis becomes integrated into the
development process earlier and earlier. Integrating programmable
logic can best address the critical timing analysis of SoC designs
when the programmable logic is in the form of a re-usable cell for
which timing has been characterized in the target foundry process.
Furthermore, there needs to be topology-specific extraction tools,
which can provide the design-specific timing characteristic data
after a block has been fully mapped to the embedded
programmable-logic cell.
Using Programmable Logic Cores
Embedded programmable-logic cores (PLCs) enable design teams to
reduce project risk by placing the high-risk parts of their designs
in programmable logic. In addition to reducing project risks, PLCs
offer the design team a way to implement different features for
different versions of a product, whether a chip or full system,
using the same chip die. Where there is a risk of changing
standards, such as in communication-system design, field
reprogrammability provides accelerated development programs, early
release to production, and low-cost, low-risk product upgrades in
the field.
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About the Author
Ralph Zak is Vice President of Marketing at
Adaptive Silicon (ASi). Prior to joining ASi in 2000, he spent most
of the past 20 years in strategic marketing and planning roles with
various EDA and semiconductor software companies including Calma,
HHB Systems, Mentor Graphics, Quickturn, and Consilium.
This viewpoint is an edited version of a paper from the Adaptive Silicon Web
site.
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