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Kal Kalbasi
Agilent EEsof EDA
TechOnline
2G, 2.5G, and 3G technologies all have a share of the wireless market and there is a strong demand to integrate all formats into each wireless handset. At the same time, there is a growing trend to integrate other wireless technologies, such as GPS and WLAN, into the handsets.
This article examines performance tradeoffs in a dual-mode phone that accommodates standards for both the Wideband Code Division Multiple Access (W-CDMA 3GPP) and Enhanced Data rates for GSM Evolution (EDGE) standards, a popular combination because of the significant existing infrastructure for these two standards. However, other multi-format phones are planned or under development. Table 1 summarizes the existing and emerging multi-format phones in various parts of the world. This variety underscores the huge design and optimization challenge to bring these products to market.
Our study of performance tradeoffs focuses on the distortions due to the digital-baseband portion in a mixed-signal environment. A simulation framework consisting of 3G signal generation, receiver down-conversion, IF sampling, data conversion, along with the digital front-end of the receiver are assembled, modeled, and characterized. The performance metric for this receiver is Error Vector Magnitude (EVM). The EVM measurement quantifies the minimum word length this receiver needs to meet the specifications, instead of depending on computationally intensive BER (bit error rate) simulations.
Three Common Receiver Architectures
Figure 1a shows the three most common architectures for receiver down-conversion:
- The classic superhetrodyne—In this commonly-used architecture, out-of-band signals are reduced by a bandpass filter placed at the antenna input, followed by a low-noise amplifier (LNA) and a mixer that converts the signal to a first IF in the range of 100 to 200 MHz. After the mixer, one or more stages of filters and amplifiers perform channel filtering. The signal is then amplified and downconverted to baseband for demodulation.
- Direct conversion—This architecture has an apparent simplicity, but it is not simple in practice. It includes an RF bandpass filter, LNA, and mixer. The mixer, however, converts directly to baseband, which requires an accurate quadrature at the local oscillator (LO), which is at the same frequency as the RF input. Other design challenges include dealing with the DC signals generated by imbalances in the mixer, which can be difficult to filter.
- DSP-based digital IF—The advantage of DSP is that channel filtering can be programmable, resulting in a single radio architecture that will adapt to multiple formats. The full bandwidth of the signal still exists after the first mixer, which must be captured by the A/D converter (commonly implemented with a bandpass sigma-delta converter). We will analyze and simulate a digital IF design supporting 3GPP and GSM/EDGE formats.
Figure 1a: Receiver architectures: superhetrodyne, direct conversion, and digital IF
In digital or zero-IF architectures, A/D conversion is followed by three main blocks:
- I-Q down-converter
- Filter
- Demodulator (Figure 1b).
Since IF processing must extract the desired signal from a wideband input, the design challenge lies in the seemingly simple quadrature and filter operations. In our example, the narrow-band signal is GSM/EDGE and the wideband signal is 3GPP.
Figure 1b: One example of a receiver architecture with a digital IF section
In 3GPP systems, the input bandwidth of the IF signal is 5 MHz. The sampling rate should be chosen such that it satisfies the baseband processing for this wideband signal. The greatest challenge is the extraction of the narrow-band GSM/EDGE signal from the wideband signal, which must perform properly in the presence of spurious, image, and blocker signals.
3GPP Channel Select Filtering
One proposed architecture for the 3GPP and GSM/EDGE formats is shown in Figure 2a. The input signal in both cases is an IF signal at 69.12 MHz, which is subsampled at 30.72 MHz. Subsampling follows the relationship Fs = (4/n)FIF with n = {1,3,5,7,9,..). In addition, the 30.72 MHz subsampling rate is equal to eight times the chip rate of the 3GPP signal, in other words, 8 * 3.84 = 31.72 MHz. This relationship between the IF frequency and sampling frequency provides considerable simplification, since the sine and cosine signals that represent the complex phasor degenerate to two simple sequences of [1 0 -1 0...] and [0 1 0 -1...].
Figure 2a: Digital IF architecture for 3GPP
The sampled A/D signal is applied to a digital mixer that uses the above sequences. Note that these sequences are effectively cosine and sine multipliers, which reduces the computational requirements. Down-sample decimation by two effectively removes the zero multipliers and brings the sampling rate Fs down to 15.36 MHz. The last filter is a simple raised cosine filter for pulse shaping based on the 3GPP standard, with a roll-off rate of 0.22 and attenuation starting at -40 dBc.
Figure 2b: Digital IF architecture for EDGE
The response of this raised cosine filter for various word lengths is shown in Figure 3. It is clear that out-of-band attenuation and droop degrade with fewer bits. The RTL or the HDL representation of this filter with a specifiable bit-width can be co-simulated with the RF and baseband portions of the design to assess the distortion it introduces. The results of the co-simulation can then be used to select the minimum (optimum) word length that does not significantly distort the signal.
Figure 3: Frequency Response of 3GPP pulse-shaping filter for different word lengths
EDGE Channel Select Filtering
The digital IF for EDGE (main blocks shown in Figure 2b) performs the task of extracting the required 200 kHz bandwidth from the 5 MHz received signal. Similar to 3GPP implementation, this starts with multiplication using a periodic sequence of ones and zeros, then down-sampling by two. This result is followed by a cascade integrator comb (CIC) filter and, finally, by a compensation filter. The up- and down-sampling is adjusted in the compensation filter stage to obtain an output at one sample per symbol, or 270.88 kHz, the symbol rate for EDGE and GSM.
The CIC filter is a highly efficient multiplier-free filter for attenuating aliasing components. The frequency response of the CIC filter can be expressed in closed form as:
where N is the order and R is the down-sampling rate. We have used N=5 and R=32 for the EDGE IF stage. For high values of R, this expression approximates the multiplication of 2N sinc functions, resulting in very low sidebands and deep nulls.
An FIR filter is used for the compensation filter, simulated with 32, 16, 14, 12, 10, and 8 bits to assess the distortions introduced. This filter is a low-pass windowed (Hamming) filter with the frequency response shown in Figure 4. The different traces are frequency responses for different bit widths, with the overall performance determined by the number of bits chosen. The choice of any of these representations requires the designer to do a trade-off analysis in order to come up with the most economical solution without jeopardizing the performance of the phone.
Figure 4: Frequency response of the EDGE compensation FIR filter for different word lengths
Receiver Error Sources
To determine the performance margins of the receiver design, the error boundaries should be established through simulation. These results are then augmented by the addition of "real world" margins, which are obtained by prototyping and testing in the design-verification stage. Receiver error sources may be the result of many factors, including:
- Synthesizer phase noise
- I-Q demodulator accuracy
- Origin offset
- Frequency offset
- Fixed-point implementation
- A/D converter nonlinearities.
This list clearly shows that the source of these errors could be in the RF, baseband, or analog portion, but we are particularly interested in quantifying the distortions due to fixed-point effects.
Receiver Measurements
Standard performance verification tests are incorporated into most digital communications standards. 3GPP and EDGE both have procedures and specifications for the in-channel and off-channel tests.
One key performance specification for a receiver is sensitivity, which is generally specified at a particular BER. Sensitivity is defined as the median level of the received signal that produces a specified BER when the signal is modulated with a specified pseudo-random binary sequence (PRBS) of data.
| EDGE |
3GPP |
| Channel Spacing |
200 kHz |
Channel Spacing |
5 MHz |
| Symbol rate |
270.83 kb/s |
Transmission Chip Rate |
3.84 Mc/s |
| Receiver Sensitivity |
-102 dBm |
Receiver Sensitivity |
-121 dBm |
| CNR for Demodulation |
9 dB |
CW Blocker Above Desired Signal |
100 dB |
| Out of Band CW Blocker Above Desired Signal |
76 dB |
Adjacent Channel Selectivity @ 5 MHz |
> 63 dB |
Table 2: Relevant EDGE and 3GPP specifications
For our dual-mode example, Table 2 summarizes the relevant specifications for EDGE and 3GPP formats. These include channel spacing, bit rate, and receiver sensitivity as well as the receiver's carrier to noise ratio (CNR) for EDGE, and continuous wave (CW) blocking and adjacent channel selectivity for 3GPP. For 3GPP, the receiver sensitivity specification is for a base station at 0.001 BER for 12.2 kbps. For the same data rate the adjacent channel selectivity requires the receiver to handle a CW signal 5 MHz from the center frequency and 63 dB above the desired signal.
Bit Error Rate vs. Error Vector Magnitude
BER refers to the fractional number of errors in data transmission, and is usually the most important digital-system quality measure. However, BER simulation and measurement have some limitations. The first is that considerable simulation time is required to determine BER with confidence, especially for systems that require high transmission accuracy. At receiver sensitivities of -102 dBm (EDGE) and -121 dBm (3GPP), BER evaluation may be an inefficient use of computational resources. Another problem is that BER provides limited diagnosis value. When the value exceeds the threshold it does not give any clues regarding the probable cause.
Error vector magnitude (EVM) is a different measurement, representing the difference between the measured and expected carrier magnitude and phase at a point in time, after compensation for timing, amplitude, frequency, phase, and DC offset. EVM is a valid measurement for pre-detection waveforms, prior to equalization. The use of EVM in these cases is to assess the distortions, even ones that may be removed in blocks that follow the IF stage. It is also important to understand that the absolute value of EVM is less important than the trend it manifests.
Interference Simulations
Adjacent channel interferers are typically large undesired signals from neighboring cells. Blockers are also undesired signals, which may be from within the same cell, offset by two channels (Figure 5). Using simulation, we want to test channel performance in the presence of adjacent channel and blocker interference. The EDGE specification makes the distinction between blockers and adjacent channel interferers, because the worst-case undesired signals are referenced to different desired signal levels.
Figure 5: EDGE blockers
Interference tests are set up by simply combining the received signal with interference and sending that sum through the IF section. The output of the digital IF, which we call the "test" signal, is compared to the reference waveform and the EVM value is computed. Since one of the objectives of the simulation is to gauge the impact of fixed-point distortions, we will use different fixed-point designs or co-simulate with HDL code that represents part or all of the digital IF section and gauge the resulting value of EVM. We can also sweep the power of the interfering adjacent channel or blocker signal to determine the channel selectivity performance of the digital IF.
The simulation of a 3GPP design includes a fixed-rate uplink source with a 12.2 kbps data traffic channel and long scrambling code. The control channels are made inactive for this test source. The source data is then pulse-shaped using a raised cosine filter, modulated, and up-converted to a frequency of 1.9 GHz. The RF signal is then split, with one signal used as the reference for the EVM measurement. The other is combined with the adjacent channel signal at the 5 MHz offset, down-converted to an IF frequency of 69.12 MHz, subsampled at 30.72 MHz with an ideal A/D converter, and used as input for the digital IF section.
Figure 6 shows a schematic of a narrow-band simulation setup. The setup includes a random bit generator driving the EDGE modulator, which includes 8PSK mapping, 3p/8 rotation, and pulse shaping with a linearized Gaussian filter. As previously described, this signal is then up-converted to a 1.9 GHz RF carrier whose spectrum is also shown. This signal is used as the waveform transmitted into the propagation channel. After reception, this signal is down-converted, subsampled, and A/D converted to drive the digital IF section.
Results and Analysis
In the narrow-band system (EDGE signal), after a high-rate (ideal) A/D conversion, the ratio of sampling-to-signal bandwidth is quite high—in this case it is 30.72 MHz/200 kHz, which is greater than 153. This means that the sampled signal could include 153 channels. The challenge is to extract one channel signal using a series of high decimations without being distorted by aliasing with adjacent channels or blocker signals.
Figure 7a shows the waveform and spectrum of an EDGE signal at different stages with weak blocker power and includes a series of plots. Starting with the top row, the output I-Q waveform is superimposed on top of the reference signal, followed by the spectrum of the signal at RF, IF, and different stages of the digital IF section. The RF spectrum is at 1.9 GHz and down-conversion brings this signal to an IF of 69.12 MHz. After this signal is sampled, mixed, and decimated by a factor of two, the desired spectral component is translated to:
69.12 - 2 x 30.72 = 7.68 MHz
Figure 7b shows the same set of plots but with blocker power 50 dB above the desired signal. In this case, the distortion in the waveforms as well as strong aliasing is evident.
After digital demodulation, the CIC filter will attenuate the effect of blockers and out-of-band interference. Figure 8 is the superposition of the signal-plus-blocker spectrum and the filtered CIC response after the out-of-band part of the spectrum has been filtered by the compensation filter. Note that the CW blocker is attenuated significantly.
Figure 8: Signal plus CW blocker and the CIC response
To verify the CIC filter performance in removing the CW blocker, a simulation is performed with a sweep of the blocker power. Power is swept from -50 to +50 dB in 10 dB steps, relative to the desired signal (Figure 9). The RMS EVM (shown on the left Y-axis) varies from about 1% to a maximum of 4% for the case with the digital IF section present. This proves the effectiveness of the CIC filter and is demonstrated quite clearly if we remove the digital IF section and sweep the CW power in the same manner. The RMS EVM begins at 1%, but grows to very high values as the CW power approaches the signal level. This trend continues to a RMS EVM of 400% for CW at 50 dB above the desired signal.
Figure 9: Simulation results for blocker-to-desired signal ratios from -50 dB to +50 dB
This simulation gives us confidence in the performance of the channel selection filtering. We now want to assess the impact of bit imprecision on the signal quality. Figure 10 shows the EVM results for nine different word lengths representing the compensation filter design. This result shows the degradation of EVM for finite word lengths less than 12 bits. This is a significant result since it defines the shortest word length for implementation in the digital IF section. With the blocker present, the nominal value of EVM increases, but the breakpoint remains the same. What is important is not the absolute value of EVM, but the point where it begins to degrade significantly.
Figure 10: EVM results for various word lengths without (a) and with (b) a blocker present
In the case of the wide bandwidth of 3GPP, the EVM simulations take longer since the number of bits (chips) to be processed is much higher. The results are essentially the same as in the narrow-band case. To see the impact of adjacent channel power for 5 and 10 MHz offset, we sweep the interfering signal power and record EVM. The results (Figure 11) show the progression of distortion measured by EVM.
Figure 11: EVM vs. adjacent channel power at 5 MHz and 10 MHz offsets
Summary
Digital IF and direct conversion have become the preferred architectures for the design of multi-mode phones. For digital IF designs, simulation of RF, analog, and baseband signals is a key part of the design process, along with a tradeoff study of different channel-selection filtering parameters. To evaluate these tradeoffs, and shorten the up-front design time, a mixed-signal simulation platform that integrates floating-point, fixed-point and HDL co-simulation, while providing access to 3G signal sources and measurements, is invaluable.
To further reduce design time, EVM can be utilized as an alternative to BER for faster simulations of receiver front-end performance. In our example, the minimum number of bits for representation of filters in digital IF section was identified using a receiver simulation that included the presence of adjacent channel and blocker interferers.
The design in this article was simulated using Agilent EEsof EDA's Advanced Design System 2002C. For more information on ADS or 3GPP W-CDMA or EDGE Wireless Design Libraries visit www.agilent.com/find/eesof.
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About the Author
Ebrahim K. Kalbasi is a Communications Application Specialist in the Agilent Comms EDA Product Generation Unit. He has more than 12 years of experience in the EDA industry in various capacities, including R&D, marketing, and application development. Mr. Kalbasi's background is in communication systems, modeling and simulation. He received his BSEE in 1977, MSEE in 1988, and PhD EE in 1991, all from the University of Kansas, Lawrence, KS.
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