William Gervasi
JEDEC
TechOnline

	ABOUT THE AUTHOR William Gervasi is the chairman of the JEDEC memory parametrics committee and has been involved with the definition of DDR SDRAM since its earliest inception. He is a corporate technology analyst and assists in the implementation of DDR controllers, systems, and support software.

The upward spiral of CPU megahertz drives the computer industry, and the hunger of these CPUs for data pressures the computer memory industry to supply ever faster random access memory (RAM) to feed these CPUs. In the past decade, the RAM roadmap included evolutionary improvements from Fast Page through Extended Data Out and most recently to Synchronous Dynamic RAM (SDRAM).

Double Data Rate (DDR) SDRAM is the latest generation of main memories for computing systems. Defined by the JEDEC international standards organization, DDR employs an evolutionary set of improvements over today's SDRAMs to provide significant improvements in performance and power.

Planning for the future of DDR is already well under way, with enhancements to DDR as well as a new evolutionary step in the future called DDR II.

Table 1:   This list of computer memory technologies shows how peak data throughput increases from generation to generation

Low Voltage Signaling
SSTL_2 is a signaling standard that references the incoming data to a reference voltage, V_REF, which at 1.25V is one half of the 2.5V I/O voltage, V_DDQ. High and low states of the input are determined as millivolts above or below V_REF.

Figure 1:  The SSTl_2 signaling standard has a reference voltage set to one half of the 2.5V I/O voltage

Differential Clocks
DDR uses a primary clock, CK, and its complement, /CK, as inputs to each memory. All DDR timing is relative to the crosspoint of CK and /CK. The traces for the differential clock pair should be routed adjacent on the computing device board to maximum the common-mode noise rejection.

Figure 2:  DDR timing is always relative to the crossover of the memory's two input clocks: CK and /CK

Source Synchronous Strobing
Clocks typically do not have the same routing and loading as data, so a data strobe, DQS, is included for each grouping of data bits. The DQS signal is intended to be routed with the data and loaded identically so that these signals, as a group, have nearly identical electrical characteristics.

Figure 3:  By including a data strobe (DQS), loaded with the data, with each group of data bits, all the signals in the group have very similar electrical characteristics

Matching Data Buses
Once the association of data bits and data strobes has been established, each grouping, for example, 8 data bits per data strobe, can be treated as though it is in its own slightly skewed time domain. However, all the groupings of 8 bits that comprise the memory controller's word width must be brought back together. This can be done inside the controller in the synchronizer that times the incoming data to the internal controller clock.

Figure 4:  By synchronizing the incoming data to an internal controller clock, you can realign the various bit-groups that comprise the various data-bus words

Understanding and Using Power States
Power consumption by a DDR SDRAM varies widely depending on the state that the memory is in. For example, while a row is activated and data is being clocked out of the device, the DDR device consumes 25 times as much power as when the row is deactivated and the outputs are not being driven. A clock-enable signal, CKE, is driven high or low to enable various power states. The time the DDR device needs to exit and enter power-saving modes and to re-enable the device to transfer data can reduce the performance of the system. Good system architecture balances the use of power states against the performance needed by the system to execute the desired tasks without burning excess power.

In general, DDR provides a 3-to-1 improvement over SDRAM in data transferred for each unit of power consumed.

DDR Chips
The 66-pin TSOP-II option provides 4, 8, or 16 bits of data per device. The by-4 option is more popular with servers, for example, the by-8 with desktop PCs, and the by-16 with notebook computers. These choices are largely due to the granularity offered by each option. For example, if all these configurations use a 64-bit data bus, the granularity would be met by 16, 8, or 4 chips respectively. In turn, assuming a 256MB DDR SDRAM, modules would carry multiples of 512MB for the by-4, 256MB for the by-8, or 128MB for the by-16.

DDR Modules The 5.25-inch dual in-line memory module, or DIMM, is well suited for the server or desktop PC markets. To balance the cost of the module against the desired system complexity, such as the number of slots available for DIMMs, modules are offered in unbuffered versions that place all the DDR SDRAMs right on the system memory bus, or registered versions that place only one load per DIMM on the system address bus independent of how many DDR SDRAMs are on the module.

For small form-factor systems such as notebooks, the small outline, or SO-DIMM, yields a smaller total memory capacity but takes much less space. For the most space constrained systems, such as subnotebooks or PDAs, the DDR MicroDIMM supports up to a gigabyte of memory capacity in a form factor half the size of the SO-DIMM.

The evolution of memory technology is accomplished in small incremental steps. Each new level of performance is achieved by balancing the cost of new features against the laws of physics and needs of faster processors. DDR makes such a set of tradeoffs, enhancing today's SDRAM with lower voltage and a handful of feature changes to enable a faster, cooler memory device.

System designers must make themselves aware of the packaging options for DDR configurations, and of the tricks and techniques to exploit this technology. They must also look to the future to be ready to migrate to the next level of performance when a new memory technology comes to market.